1. Field of the Invention
The present invention relates to a phase locked loop (PLL) circuit and a frequency pull-in method therefor.
2. Description of Related Art
FIG. 1 shows a basic structure of a PLL circuit used commonly.
In FIG. 1, a phase comparator 92 performs a phase comparison between a reference frequency signal from a quartz oscillator 91 and an output signal of the PLL circuit, and a phase error signal representing the phase error between those signals is supplied to a low-pass filter (LPF) 93 so that a low frequency component of the phase error signal is supplied to a voltage controlled oscillator (VCO) 94. The VCO 94 oscillates at a frequency responsive to the supplied low-frequency component of the phase error signal. The output signal of the VCO is used as the output signal of the PLL circuit and also supplied to the phase comparator 92. With the structure described above, the PLL circuit produces the output signal which is synchronized in phase with the reference frequency signal.
However, as shown in FIG. 2, the pull-in (lock-in) to the reference frequency f.sub.0 may not be performed surely if the difference between the reference frequency f.sub.0 of the quartz oscillator 91 and the oscillation frequency of the VCO 94 is large at an initial stage of the operation of the PLL circuit. To cope with this problem, it is conceivable to set an input voltage of the VCO 94 to a voltage by which the oscillation frequency of the VCO is forcibly controlled to an oscillation frequency f.sub.VCO, near to the reference frequency f.sub.0 until the PLL circuit locks.
More particularly, as shown in FIG. 3, it is conceivable to provide an adder 95 and a voltage outputting circuit 96, thereby to add a voltage to forcibly pull-in the PLL circuit to the input voltage of the VCO 94. However, if the frequency error between the reference frequency and the oscillation frequency of the VCO is not detected, it is not possible to derive the voltage value for the forcible pull-in operation suited for the frequency error value. Therefore in the scheme depicted in FIG. 3, a number of voltage values for the forcible pull-in of the PLL circuit are stored in a bank memory 96a, in the voltage outputting circuit 96. One of the voltage values stored in the bank memory 96a is in turn selected by means of a selector 96b, so that the voltage of the selected value is supplied to the adder 95, to perform an attempt of the pull-in to the reference frequency f.sub.0. For assuring the usability of the PLL circuit for various reference oscillators, it is required that the bank memory 96a is writable from outside, and has a capacity sufficient for storing numerous voltage values.
As explained above, the frequency pull-in scheme shown in FIG. 3 has a drawback that the complexity of the structure and the scale of the circuit will inevitably be increased when it is sought to broaden the width of the use of the circuit.